Bayesian neural networks to analyze hyperspectral datasets using uncertainty metrics

Machine learning techniques, and specifically neural networks, have proved to be very useful tools for image classification tasks. Nevertheless, measuring the reliability of these networks and calibrating them accurately are very complex. This is even more complex in a field like hyperspectral imaging, where labeled data are scarce and difficult to generate. Bayesian neural networks (BNNs) allow to obtain uncertainty metrics related to the data processed (aleatoric), and to the uncertainty generated by the model selected (epistemic). On this work, we will demonstrate the utility of BNNs by analyzing the uncertainty metrics obtained by a BNN over five of the most used hyperspectral images datasets. In addition, we will illustrate how these metrics can be used for several practical applications such as identifying predictions that do not reach the required level of accuracy, detecting mislabeling in the dataset, or identifying when the predictions are affected by the increase of the level of noise in the input data

An Efficient Hardware Accelerator to Handle Compressed Filters and Avoid Useless Operations in CNNs

Due to sparsity, a significant percentage of the operations carried out in Convolutional Neural Networks (CNNs) contains a zero in at least one of their operands. Different approaches try to take advantage of sparsity in two different ways. On the one hand, sparse matrices can be easily compressed, saving space and memory bandwidth. On the other hand, multiplications with zero in their operands can be avoided. We propose the implementation in an FPGA of an architecture for CNNs capable of taking advantage of both, sparsity and filter compression.    Due to sparsity, a significant percentage of the operations carried out in Convolutional Neural Networks (CNNs) contains a zero in at least one of their operands. Different approaches try to take advantage of sparsity in two different ways. On the one hand, sparse matrices can be easily compressed, saving space and memory bandwidth. On the other hand, multiplications with zero in their operands can be avoided. We propose the implementation in an FPGA of an architecture for CNNs capable of taking advantage of both, sparsity and filter compression.     &nbsp

Isotope dilution analysis for particle mass determination using single-particle inductively coupled plasma time-of-flight mass spectrometry: application to size determination of silver nanoparticles

This paper describes methodology based on the application of isotope dilution (ID) in single-particle inductively coupled plasma time-of-flight mass spectrometry (spICP-ToFMS) mode for the mass determination (and sizing) of silver nanoparticles (AgNPs). For this purpose, and considering that the analytical signal in spICP-MS shows a transient nature, an isotope dilution equation used for online work was adapted and used for the mass determination of individual NPs. The method proposed measures NP isotope ratios in a particle-to-particle approach, which allows for the characterization of NP mass (and size) distributions and not only the mean size of the distribution. For the best results to be obtained, our method development (undertaken through the analysis of the reference material NIST RM 8017) included the optimization of the working conditions for the best precision and accuracy in isotope ratios of individual NPs, which had been only reported to date with multicollector instruments. It is shown that the precision of the measurement of these ratios is limited by the magnitude of the signals obtained for each NP in the mass analyzer (counting statistics). However, the uncertainty obtained for the sizing of NPs in this approach can be improved by careful method optimization, where the most important parameters are shown to be the selection of the spike isotopic composition and concentration. Although only AgNPs were targeted in this study, the method presented, with the corresponding adaptations, could be applied to NPs of any other composition that include an element with different naturally available isotopes

Accelerating board games through Hardware/Software Codesign

Board games applications usually offer a great user experience when running on desktop computers. Powerful high-performance processors working without energy restrictions successfully deal with the exploration of large game trees, delivering strong play to satisfy demanding users. However, nowadays, more and more game players are running these games on smartphones and tablets, where the lower computational power and limited power budget yield a much weaker play. Recent systems-on-a-chip include programmable logic tightly coupled with general-purpose processors enabling the inclusion of custom accelerators for any application to improve both performance and energy efficiency. In this paper, we analyze the benefits of partitioning the artificial intelligence of board games into software and hardware. We have chosen as case studies three popular and complex board games, Reversi, Blokus, and Connect6. The designs analyzed include hardware accelerators for board processing, which improve performance and energy efficiency by an order of magnitude leading to much stronger and battery-aware applications. The results demonstrate that the use of hardware/software codesign to develop board games allows sustaining or even improving the user experience across platforms while keeping power and energy low

Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 FPGA

In this paper we have evaluated the overhead and the tradeoffs of a set of components usually included in a system with run-time partial reconfiguration implemented on a Xilinx Virtex-5. Our analysis shows the benefits of including a scratchpad memory inside the reconfiguration controller in order to improve the efficiency of the reconfiguration process. We have designed a simple controller for this scratchpad that includes support for prefetching and caching in order to further reduce both the energy and latency overhead

A Replacement Technique to Maximize Task Reuse in Reconfigurable Systems

Dynamically reconfigurable hardware is a promising technology that combines in the same device both the high performance and the flexibility that many recent applications demand. However, one of its main drawbacks is the reconfiguration overhead, which involves important delays in the task execution, usually in the order of hundreds of milliseconds, as well as high energy consumption. One of the most powerful ways to tackle this problem is configuration reuse, since reusing a task does not involve any reconfiguration overhead. In this paper we propose a configuration replacement policy for reconfigurable systems that maximizes task reuse in highly dynamic environments. We have integrated this policy in an external taskgraph execution manager that applies task prefetch by loading and executing the tasks as soon as possible (ASAP). However, we have also modified this ASAP technique in order to make the replacements more flexible, by taking into account the mobility of the tasks and delaying some of the reconfigurations. In addition, this replacement policy is a hybrid design-time/run-time approach, which performs the bulk of the computations at design time in order to save run-time computations. Our results illustrate that the proposed strategy outperforms other state-ofthe-art replacement policies in terms of reuse rates and achieves near-optimal reconfiguration overhead reductions. In addition, by performing the bulk of the computations at design time, we reduce the execution time of the replacement technique by 10 times with respect to an equivalent purely run-time one